VLSI Workshop - (Get Internship Opportunity)

​The VLSI workshop will begin with an opening speech from 10:00 am to 11:00 am, setting the stage for an engaging and insightful session. This will be followed by the technical segment from 11:00 am to 1:00 pm, led by experienced speakers Sarath, Naresh, and Saravana. They will cover essential aspects of the VLSI design process with a focus on core industry practices.

​Technical Topics Covered

• ​Overview of ASIC Flow: Introduction to the complete process from specification to fabrication.

• ​PNR Steps: Detailed explanation of Place-and-Route methodology.

• ​Floorplan: Strategies for chip area allocation and optimization.

• ​Powerplan: Techniques for ensuring reliable power distribution across the chip.

• ​Placement: Best practices for arranging standard cells and macros.

• ​CTS (Clock Tree Synthesis): Approaches for achieving optimal clock distribution.

• ​Routing: Methods for signal and interconnect design implementation.

• ​Signoff Checks: Final verification steps to ensure design readiness for tape-out.

​This workshop aims to provide participants with practical knowledge of the VLSI design flow, industry-relevant tools, and hands-on insights from domain experts.